This application claims priority from Korean Patent Application No. 2002-74376, filed on 27 Nov. 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an arbiter and a method of controlling the same, and more particularly, to a programmable fixed priority and a round robin arbiter and a method of controlling a bus therein.
2. Description of the Related Art
As the speed of a system clock increases with the development of high-speed and high-performance system-on-a-chip (SOC) circuits, the speed or performance of an arbitrator, which arbitrates bus occupations of master blocks in a bus system, has improved.
In general, the arbiter performs bus arbitration for master function blocks connected to a bus. Bus arbitration is an operation under which, when any master block transmits a request signal including information related to a request for use of the bus, to the arbiter, the arbiter receives the request signal from the master block or blocks and outputs a bus master grant signal including information related to a grant for use of the bus, in a predetermined order. In this manner, each of the master blocks can transmit data over the bus.
Conventional arbiters can support both a programmable fixed priority mode and a round robin mode, the mode being user selectable.
In the fixed priority mode, after each master block transmits the request signal to the arbiter, the arbiter, which has been previously programmed to assign different priorities to the master blocks, outputs the bus master grant signal to a master block having the highest priority.
In the round robin mode, the arbiter equally assigns priority to each of the master blocks according to pointer information. That is, in the round robin mode, the arbiter assigns the lowest priority to the master block that has the highest priority and receives the bus master grant signal, and then, assigns the highest priority to a master block whose priority is lower than the master block that receives the bus master grant signal.
FIG. 1 is a block diagram of a conventional arbiter.
Referring to FIG. 1, the conventional arbiter includes a request-reordering logic 110, a first multiplexer (MUX) 120, a request-selecting logic 130, a grant-reordering logic 140, a second multiplexer (MUX) 150, a request-rotating logic 160, and a grant-rotating logic 170.
The request-reordering logic 110 reorders requested priorities of the master blocks and outputs a request-reordering signal so that the priorities can be in accordance with priority information of the master blocks stored in a programmable priority register, referred to herein as an “HPRIF” register. Here, the priorities of the master blocks can be programmed into the HPRIF register.
Here, the priorities of the master blocks can be programmed into the HPRIF register.
The first multiplexer (MUX) 120 selectively outputs the request-reordering signal in the programmable fixed priority mode or the round robin mode.
The request-selecting logic 130 outputs a bus master-selecting signal according to the priorities in response to input request-reordering signals.
The grant-reordering logic 140 outputs a bus master grant signal according to the priorities in response to the bus master-selecting signal.
The second multiplexer (MUX) 150 selectively outputs a bus master grant signal in the programmable fixed priority mode or the round robin mode.
The request-rotating logic 160 rotates requested priorities in a direction based on pointer information indicating which master block currently has the highest priority, reorders the requested priorities, and outputs the request-reordering signal. That is, the request-rotating logic 160 used in the round robin mode does not reorder the priorities based on priority information stored in the HPRIF register but rather reorders the priorities based on the pointer information. Therefore, it is not possible for the arbiter to give priority to a master block for occupation of a bus not used by other master blocks.
The grant-rotating logic 170 rotates a grant priority in a direction based on the bus master-selecting signal and outputs a bus master grant signal according to the priorities.
FIG. 2 is a flowchart illustrating the operation of the conventional arbiter of FIG. 1 operating in a fixed priority mode.
Referring to FIG. 2, when the conventional arbiter is set to the fixed priority mode, the first multiplexer (MUX) 120 and the second multiplexer (MUX) 150 are also set to the fixed priority mode. In addition, fields HPRIF0, HPRIF1, HPRIF2, and HPRIF3 of a HPRIF register which stores priorities of the master blocks (master 3, master 0, master 2, and master 1) are sequentially stored (step S210). Here, HPRIF0 stores priority information on a master block having the highest priority and HPRIF3 stores priority information on a master block having the lowest priority. In this example, the master block having the highest priority is fixed as master 3.
Since the request-reordering logic 110 has to reorder the requested priorities of the master blocks according to priority information stored in the HPRIF register when a delayed request signal is input from a master block, the request-reordering logic 110 outputs the request-reordering signal to give the highest priority to the master block if the request signal is input from master 3 and give a lower priority to the master block if the request signal is input from one of the other master blocks (step S220). Then, the request-selecting logic 130 outputs the bus master-selecting signal according to the priorities such that weight is given to master 3 in response to the request-reordering signal (step S230). The grant-reordering logic 140 outputs the bus master grant signal according to the priorities such that weight is given to master 3 in response to the bus master-selecting signal (step S240). Thus, the master block receiving the bus master grant signal can occupy the bus.
FIG. 3 is a flowchart showing the conventional arbiter of FIG. 1 operating in the round robin mode. FIG. 4 is a view for explaining operations of the conventional arbiter of FIG. 1 in the round robin mode in more detail.
Referring to FIGS. 3 and 4, when the conventional arbiter is set to the round robin mode, the first multiplexer (MUX) 120 and the second multiplexer (MUX) 150 are set to the round robin mode, and a predetermined pointer points to ‘1’ (step S310), which means that the highest priority is given to master 1.
Here, if the delayed request signal is input from the master block, the request-rotating logic 160, in response to the pointer pointing master 1 that currently has the highest priority, rotates the requested priorities in the direction shown in FIG. 4 and reorders the requested priorities of the master blocks. Therefore, the request-rotating logic 160 outputs the request-reordering signal such that the request-rotating logic 160 gives the highest priority to the master block if the request signal is input from master 1 and gives a lower priority to the master block if the request signal is input from one of the other masters (step S320). The request-selecting logic 130 outputs the bus master-selecting signal according to the priorities such that the request-selecting logic 130 gives the highest priority to master 1 in response to the request-reordering signal (step S330). The grant-rotating logic 170 outputs the bus master grant signal according to the priorities in response to the bus master-selecting signal such that it rotates the grant priorities in the direction shown in FIG. 4 and gives the highest priority to master 1 (step S340). Thus, the master block receiving the bus master grant signal can occupy the bus. Here, if the bus master grant signal is output to a master block, the lowest priority is given to the master that had the highest priority, and the pointer increases by 1. Thus, the highest priority is given to master blocks in an order shown in FIG. 4. Therefore, the master blocks each have an opportunity of being assigned the highest priority.
In the conventional arbiter, the request-selecting logic 130 can be used in both the fixed priority mode and the round robin mode. However, the request-reordering logic 110 and the grant-reordering logic 140 used in the fixed priority mode are different from the request-rotating logic 160 and the grant-rotating logic 170 used in the round robin mode. Therefore, in the conventional arbiter, additional first and second multiplexers 120 and 150 are needed to select the fixed priority mode or the round robin mode as shown in FIG. 1. Thus, the circuit becomes more complicated and processing speed goes down.
Since some signals are applied to the request-reordering logic 110 and the grant-reordering logic 140 in the fixed priority mode and to the request-rotating logic 160 and the grant-rotating logic 170 in the round robin mode regardless of the operation mode of the arbiter, a circuit operating in another mode consumes power even when the arbiter operates in a certain mode. In particular, the fixed priority mode consumes a lot of power because the request-rotating logic 160 and the grant-rotating logic 170 are operated unnecessarily.
In addition, when the request signal input from the master block drives both the request-reordering logic 110 and the request-rotating logic 160, loads increase and the processing speed becomes slow due to the delayed signal. When the bus master-selecting signal output from the request-selecting logic 130 drives both the grant-reordering logic 140 and the grant-rotating logic 170, loads increase and the processing speed becomes slow due to the delayed signal.
Since the conventional arbiter rotates the requested priority and the grant priority according to a predetermined order in the round robin mode, it is not possible to give the priority to a master for occupation opportunity of the bus not used by other master blocks.